There are situations that have become more common in which a system clock is operated at a frequency well below the capability of the memory that is part of the system. The memory may even have the ability to operate at twice the frequency of the system clock. This situation can arise, for example, in the case of a cache embedded in the same integrated circuit as a processor. One technique for taking advantage of this ability of a memory is to multiply the system clock and use the multiplied clock for operating the memory. To double the frequency while keeping the clock operating properly, the master clock should not merely be doubled but quadrupled then divided by two. This will typically require an additional phase locked loop (PLL). PLLS are relatively large circuits, and their power consumption is proportional to frequency. Thus, the likely requirement of an additional PLL that operates at four times the master clock frequency requires costly additional space and significant extra power.
Thus, there is a need to reduce or remove the disadvantages of increasing a memory's operating frequency from that of a master clock.